DK-DEV-5SGXEA7N【PDF 16/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51002

2014.01.10

ALM Operating Modes

1-7

The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output

while the register drives another output.

Register packing improves device utilization by allowing unrelated register and combinational logic to be

packed into a single ALM. Another mechanism to improve fitting is to allow the register output to feed back

into the look-up table (LUT) of the same ALM so that the register is packed with its own fan-out LUT. The

ALM can also drive out registered and unregistered versions of the LUT or adder output.

Figure 1-7: ALM Connection Details for Stratix V Devices

syncload

aclr[1:0]

dataf0

datae0

shared_arith_in

carry_in

clk[2:0] sclr

dataa

datab

datac0

4-Input

LUT

GND

3-Input

LUT

+

D

CLR

Q

Row, Column

Direct Link Routing

3

3-Input

LUT

D

CLR

Q

Row, Column

Direct Link Routing

datac1

4-Input

LUT

3

3-Input

+

D

CLR

Q

Row, Column

Direct Link Routing

LUT

3-Input

LUT

VCC

D

CLR

Q

Row, Column

Direct Link Routing

datae1

dataf1

shared_arith_out

carry_out

ALM Operating Modes

The Stratix V ALM operates in any of the following modes:

? Normal mode

? Extended LUT mode

? Arithmetic mode

Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices

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